This application is based on and incorporates herein by reference Japanese Patent Application No. 2002-21971 filed on Jan. 30, 2002.
The present invention relates to a memory controller for controlling a memory by utilizing serial data.
An EEPROM (Electrically Erasable and Programmable Read Only Memory) is known as a non-volatile memory which can electrically program new data by erasing old data. Since this EEPROM is designed small in size to easily program various data, it is widely used in a system utilizing a microcomputer for various purposes such as mode setting, storage of ID code and displacement of dip switch.
Particularly when a small amount of data is stored in this EEPROM, a serial interface is used for making access to the EEPROM. In this case, a memory controller is required for decoding a command part in serial data which has been serially inputted, converting address part and data part in the serial data to a parallel data to supply this parallel data to the EEPROM, and outputting the parallel data read from the EEPROM through conversion into the parallel data.
This memory controller is usually constructed to receive a clock signal, a chip enable signal, and a reset signal as input signals in addition to serial data; obtain, depending on a clock, the serial data supplied during an active period in which the chip enable signal is inputted; and execute access to the EEPROM depending on contents of the thus obtained serial data.
However, assuming that such a memory controller is used, if noise is superimposed on the input signal due to irregularity generated in a power source voltage or static electricity or the like, it is likely that an unexpected access (writing to non-related addresses and generation of erase instruction, etc.) to the EEPROM is executed, and various important data are destroyed. This might cause uncontrollable program execution or unrecoverable system failure.
For example, serial data xe2x80x98110001101100010xe2x80x99 is considered here. This serial data is inputted for writing the data xe2x80x9801100010xe2x80x99 to the address xe2x80x980011xe2x80x99 when a command expressing a write instruction is defined as xe2x80x98110.xe2x80x99
As illustrated in FIG. 9A, when noise is mixed in a chip enable signal CE in a period (slot S) corresponding to the fourth clock, a data train of the slots S1 to S3 fetched before this period is cancelled. However, since the chip enable signal CE is continuously inputted even after the influence of noise is eliminated, acquisition of data is started again. As a result, since data of the slot S6 is erroneously recognized as the leading data of serial data DIO, unexpected memory access different from expected access of a user is executed under the assumption that a write instruction (WRI) of the data xe2x80x98010XXXXXxe2x80x99 to the address (ADR) xe2x80x981100xe2x80x99 is generated.
Moreover, as illustrated in FIG. 9B, when noise is also mixed in a reset signal RST, a probability of erroneous recognition of instruction also occurs as described above. It is because, since an apparatus is reset with noise mixed in the reset signal RST, a data train of slots S1 to S3 fetched before the reset is cancelled and if the chip enable signal CE is inputted continuously even after the reset by noise is eliminated, data fetch is started again.
It is therefore an object of the present invention to provide a memory controller and a serial memory which can prevent memory access which is executed due to an adverse effect of noise and is different from the access intended by a user.
In a memory controller according to the present invention, at least serial data including an instruction bit train with addition of a start bit at the beginning thereof, a clock signal synchronized to this serial data, a chip enable signal for designating the relevant apparatus, and a reset signal for resetting the relevant apparatus are inputted.
During the active period in which the chip enable signal is being inputted, the serial data is stored depending on the clock signal and an enabling signal is generated based on the end timing of active period. Thereby, memory access is executed depending on contents of the instruction bit train. However, when the relevant apparatus is reset during the active period, generation of the enabling signal based on the end timing of the active period is inhibited.
That is, it never occurs that memory access which is different from the access expected by a user is executed based on contents of the fetched serial data even if the serial data is fetched from the intermediate part because the relevant apparatus is reset when noise is mixed in the reset signal during the active period and the preceding active period is still lasted even after such a reset state is eliminated. This can surely prevents programming of contents stored in the memory to contents different from the one expected by a user based on erroneous operation caused by noise mixed in the reset signal.